OAL_CACHE_INFO (Windows Embedded CE 6.0)

1/5/2010

This structure stores information about the cache.

Syntax

typedef struct {
    UINT32 L1Flags;
    UINT32 L1ISetsPerWay;
    UINT32 L1INumWays;
    UINT32 L1ILineSize;
    UINT32 L1ISize;
    UINT32 L1DSetsPerWay;
    UINT32 L1DNumWays;
    UINT32 L1DLineSize;
    UINT32 L1DSize;
    UINT32 L2Flags;
    UINT32 L2ISetsPerWay;
    UINT32 L2INumWays;
    UINT32 L2ILineSize;
    UINT32 L2ISize;
    UINT32 L2DSetsPerWay;
    UINT32 L2DNumWays;
    UINT32 L2DLineSize;
    UINT32 L2DSize;
} OAL_CACHE_INFO;

Members

• L1Flags
  Flags for the level 1 (L1) cache. The following table shows the valid flags for this member.

  Flag	Description
  CF_UNIFIED	Specifies that the instruction (I) and data (D) caches are unified.
  CF_WRITETHROUGH	Specifies that the cache is in write-through mode. If this flag is not set, the cache is in write-back mode.
  CF_COHERENT	Specifies that no cache flush operations are necessary.

• L1ISetsPerWay
  Specifies the number of sets per way for the L1 instruction cache.

• L1INumWays
  Specifies the number of ways for the L1 instruction cache, 1 for direct-mapped.

• L1ILineSize
  Line size of the L1 instruction cache, in bytes. This is typically the width of the data bus between cache memory and main memory.

• L1ISize
  Total size of the L1 instruction cache, in bytes.

• L1DSetsPerWay
  Specifies the number of sets per way for the L1 data cache.

• L1DNumWays
  Specifies the different types of cache organization for the L1 data cache. For direct-mapped, use 1.

• L1DLineSize
  Line size of the L1 data cache, in bytes. This is typically the width of the data bus between cache memory and main memory.

• L1DSize
  Total size of the L1 data cache, in bytes.

• L2Flags
  Flags for the level 2 (L2) cache.

  The following flags are valid for this member.

  Flag	Description
  CF_UNIFIED	Specifies that the instruction (I) and data (D) caches are unified.
  CF_WRITETHROUGH	Specifies that the cache is in write-through mode. If this flag is not set, the cache is in write-back mode.
  CF_COHERENT	Specifies that no cache flush operations are necessary.

• L2ISetsPerWay
  Specifies the number of sets per way for the L2 instruction cache.

• L2INumWays
  Specifies the number of ways for the L2 instruction cache, 1 for direct-mapped.

• L2ISize
  Total size of the L2 instruction cache, in bytes. A size of 0 (zero) means that there is no L2 instruction cache.

• L2ILineSize
  Line size of the L2 instruction cache, in bytes. This is typically the width of the data bus between cache memory and main memory.

• L2DSetsPerWay
  Specifies the number of sets per way for the L2 data cache.

• L2DNumWays
  Specifies the different types of cache organization for the L2 data cache. For direct-mapped, use 1.

• L2DLineSize
  Line size of the L2 data cache, in bytes. This is typically the width of the data bus between cache memory and main memory.

• L2DSize
  Total size of the L2 data cache, in bytes. A size of 0 (zero) means that there is no L2 data cache.

Remarks

Use the g_oalCacheInfo global variable as a pointer to this structure.

Requirements

See Also

Reference

Cache Structures