Core OS Best Practices (Windows Embedded CE 6.0)
1/6/2010
This topic describes best practices for working with the ARMv4 and ARMv5 microprocessors.
ARMv4 and ARMv5 Best Practices
ARM processors with either version 4 or version 5 architecture have virtually index or virtually tagged caches. Therefore, cache line collisions or aliasing problems can occur. To prevent these problems the kernel uncaches any pages that can cause this problem. It also uses copy-in/copy-out for all pointer parameters in user mode system calls and all calls to CeAllocAsyncBuffer.
For more information on CEAllocAsyncBuffer, see AsynchronousBuffer_t.
The following list shows the best practices for working with ARMv4 and ARMv5 microprocessors:
- Avoid aliasing.
- Avoid calling CeMapCallerPtr directly, unless it is unavoidable.
- Use marshal helper APIs to allow the operating system to determine the balance point between aliasing and copy-in/copy-out.
- Use CeFlushAsyncBuffer to flush asynchronous buffers to the caller if you need to the caller to see the change immediately. For more information on CeFlushAsyncBuffer, see AsynchronousBuffer_t.
- Do not create aliases with VirtualCopy.
- Call VirtualCopy only with the fdwProtect parameter set to PAGE_PHYSICAL.
- Avoid overlapping views to the same map file.
- Overlapped views cause access to the map file to be uncached.
The only functions that track aliases are CeMapCallerPtr, the marshal helper functions, and the VirtualAllocCopyEx function. For more information on the marshal helper functions, see Kernel Buffer Marshaling Reference.
ARMv6 and ARMv7 Best Practices
Do not use fast interrupt mode on ARMv6 and ARMv7 microprocessors. For details, see Fast Interrupt Mode on ARMv6 and ARMv7 Microprocessors Not Supported.