MIPS-specific Options
The following table shows compiler switches for MIPS microprocessors.
Option | Description |
---|---|
/QMRWCE | Generates code that will run on any windows CE-based MIPS platform running in 32-bit mode with floating point emulation. For more information, see /QMRWCE, /QMRFWCE - Generate Code for Windows CE. |
/QMRFWCE | Generates code that will run on any Windows CE–based MIPS platform running in 32-bit mode with a floating point unit For more information, see /QMRWCE, /QMRFWCE - Generate Code for Windows CE. |
/QMmips1, /QMmips2, /QMmips3, /QMmips4, /QMmips5, /QMmips32, and /QMmips64 | Generates code for MIPS I, II, III, IV, V, 32, and 64 ISAs. For more information, see /QMmipsNN - Generate code for specific MIPS ISA. |
/QMmips16 - Generate Code for MIPS16 ASE | Generates code for MIPS16 ASE. |
/QMFPE, /QMFPE - Floating Point Emulation | Enables Floating Point emulation, using floating-point hardware. |
/QMR3900 | Allows Phillips PR3900 MIPS chip inline assembler instructions, generate code for MIPS II. For more information, see /QMRnnnn -Optimize for specific MIPS chip. |
/QMR4100 | Allows NEC VR4100 MIPS chip inline assembler instructions, generate code for MIPS II. For more information, see /QMRnnnn -Optimize for specific MIPS chip. |
/QMR4200 | Allows NEC VR4200 MIPS chip inline assembler instructions, generate code for MIPS II. For more information, see /QMRnnnn -Optimize for specific MIPS chip. |
/QMR4300 | Allows NEC VR4300 MIPS chip inline assembler instructions, generate code for MIPS IV with floating point hardware. For more information, see /QMRnnnn -Optimize for specific MIPS chip. |
/QM5400 | Allows NEC VR5400 MIPS chip inline assembly instructions, generate code for MIPS IV with floating point hardware. For more information, see /QMRnnnn -Optimize for specific MIPS chip. |
See Also
Compiler Setup Mechanisms | Compiler Options | General-Purpose Compiler Options | ARM-specific Options | Hitachi-specific Options | MIPS Guide
Last updated on Thursday, April 08, 2004
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