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SH3-DSP Instructions

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You can enable DSP support through a command line option to the SHx assembler, Shasm. The -Qdsp command line option specifies the SH3-DSP as the target Hitachi SH CPU for a source program that contains DSP instructions to assemble. This selects the set of registers and instructions that the assembler recognizes. For more information about Shasm, see SHx Series Assembler Directives. For more information about command line options, see Compiler Options.

When you enable DSP support, Shasm recognizes the SH3-DSP instructions in addition to the instructions available on the SH-3 and SH-3e. The following list shows the categories of instructions added:

  • ALU Fixed Decimal Point Operations: These are fixed-decimal-point operations with either 40-bit with guard bits or 32-bit fixed decimal point data. These include addition, subtraction, and comparison instructions.
  • ALU Integer Operations: These are integer arithmetic operations with either 24-bit with guard bits or 16-bit integer data. They include increment and decrement instructions.
  • ALU Logical Operations: These are logical operations with 16-bit logical data. They include AND, OR, and exclusive OR.
  • Fixed Decimal Point Multiplication: This is fixed-decimal-point multiplication of the top 16 bits of fixed decimal point data. Condition bits such as the DC bit are not updated.
  • Shift Operations: These are arithmetic and logical shift operations. Arithmetic shift operations are arithmetic shifts of 40 bits with guard bits or 32 bits with no guard bits of fixed decimal point data. Logical shift operations are logical operations on 16 bits of logical data. The amount of the arithmetic shift operation is –32 to +32, negative for right shifts, positive for left shifts. For logical shifts, the amount is –16 to +16.
  • MSB Detection Instruction: This operation finds the amount of the shift to normalize the data. It finds the position of the MSB bit in either 40-bit with guard bits or 32-bit fixed decimal point data as either 24 bit with guard bits or 16 bit integer data.
  • Rounding Operation: This operation rounds 40-bit fixed decimal point data with guard bits to 24 bits or 32-bit with no guard bits fixed decimal point data to 16 bits.
  • Data Transfers: Data transfers consist of X and Y data transfers, which load or store 16-bit data to and from X and Y memory, and single data transfers, which load and store 16- or 32-bit data from all memories. Two X and Y data transfers can be processed in parallel. Condition bits such as the DC bit are not updated.

The operation instructions include both conditional operation instructions and instructions that are conditionally executed depending on the DC bit. Conditional instructions do not update condition bits such as the DC bit. Their settings vary for arithmetic operations, logical operations, arithmetic shifts, and logical shifts, or MSB detection instructions and rounding instructions, set the condition bits like for arithmetic operations. Arithmetic operations include overflow, preventing instructions such as saturation operations. When the S bit in the SR register specifies a saturation operation, the maximum or minimum value is stored when the result of operation overflows.

See Also

SH-3 Calling Sequence Specification | SH3-DSP Calling Sequence Specifications | SH3-DSP Documentation Disclaimer | SH3-DSP Registers | SH3-DSP Data Formats

 Last updated on Thursday, April 08, 2004

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