Share via


New SHx Assembler Instructions

When SH-4 support is enabled, SHASM recognizes the SH-4 floating-point instructions in addition to the instructions available on the SH-3 and SH-3e. These include:

The following table shows new data transfer instructions.

Instruction Affected register
OCBI @Rn
OCBP @Rn
OCBWB @Rn
MOVCA.L R0, @Rn

The following table shows new double-precision floating-point instructions.

Instruction Affected register
FABS.D DRn
FADD.D DRm,DRn
FCMP/EQ.D DRm,DRn
FCMP/GT.D DRm,DRn
FCNVDS DRm,FPUL
FCNVSD FPUL,DRn
FDIV.D DRm,DRn
FLOAT.D FPUL,DRn
FMUL.D DRm,DRn
FNEG.D DRn
FSQRT.D DRn
FSUB.D DRm,DRn
FTRC.D DRm,FPUL
FMOV.D DRm,DRn
FMOV.D @Rm,DRn
FMOV.D @Rm+,DRn
FMOV.D @(R0,Rm),DRn
FMOV.D DRm,@Rn
FMOV.D DRm,@-Rn
FMOV.D DRm,@(R0,Rn)
FMOV.D DRm,XDn
FMOV.D XDm,DRn
FMOV.D XDm,XDn
FMOV.D @Rm,XDn
FMOV.D @Rm+,XDn
FMOV.D @(R0,Rm),XDn
FMOV.D XDm,@Rn
FMOV.D XDm,@-Rn
FMOV.D XDm,@(R0,Rn)
FIPR FVm,FVn
FTRV XMTRX,FVn
FRCHG  
FSCHG  

The following table shows new private instructions.

Instruction Affected register
FSCA FPUL,DRn
FSRRA.S FRn

The following table shows new single-precision floating-point instructions.

Instruction Affected register
FMAC.S FR0, FRm, FRn

The following table shows new system control instructions.

Instruction Affected register
STC SGR,Rn
STC.L SGR,@-Rn
STC DBR,Rn
STC.L DBR,@-Rn
LDC Rm, DBR
LDC.L @Rm+,DBR

.S or .s indicates single precision and .D or .d indicates double precision. In addition, if SH-1, SH-2, SH-3, or SH-3e is selected, SHASM generates a message for any of the new SH-4 instructions.

See Also

What's New for SH-4 | Differences Between SHASM and Hitachi Assembler | SHx Assembler Programming Limitations | New SHx Assembler Registers

 Last updated on Thursday, April 08, 2004

© 1992-2003 Microsoft Corporation. All rights reserved.