Pipeline access to tiled resources
Tiled resources can be used in shader resource views (SRV), render target views (RTV), depth stencil views (DSV) and unordered access views (UAV), as well as some bind points where views aren't used, such as vertex buffer bindings. For the list of supported bindings, see Tiled resource creation parameters. Copy* operations also work on tiled resources.
If multiple tile coordinates in one or more views is bound to the same memory location, reads and writes from different paths to the same memory will occur in a non-deterministic and non-repeatable order of memory accesses.
If all tiles behind a memory access footprint from a shader are mapped to unique tiles, behavior is identical on all implementations to the surface having the same memory contents in a non-tiled fashion.
This section provides more info about pipeline access to tiled resources.
In this section
| Topic | Description |
|---|---|
| SRV behavior with non-mapped tiles |
Behavior of shader resource view (SRV) reads that involve non-mapped tiles depends on the level of hardware support. |
| UAV behavior with non-mapped tiles |
Behavior of unordered access view (UAV) reads and writes depends on the level of hardware support. |
| Rasterizer behavior with non-mapped tiles |
This section describes rasterizer behavior with non-mapped tiles. |
| Tile access limitations with duplicate mappings |
This section describes tile access limitations with duplicate mappings. |
| Tiled resources texture sampling features |
This section describes tiled resources texture sampling features. |
| HLSL tiled resources exposure |
New Microsoft High Level Shader Language (HLSL) syntax is required to support tiled resources in Shader Model 5. |