PCI_COMMON_CONFIG (Compact 2013)

3/26/2014

This structure describes the PCI configuration space for PCI devices.

Syntax

typedef struct _PCI_COMMON_CONFIG {
  USHORT VendorID; 
  USHORT DeviceID; 
  USHORT Command; 
  USHORT Status;
  UCHAR RevisionID; 
  UCHAR ProgIf; 
  UCHAR SubClass; 
  UCHAR BaseClass; 
  UCHAR CacheLineSize; 
  UCHAR LatencyTimer; 
  UCHAR HeaderType; 
  UCHAR BIST;  
  union {
    struct _PCI_HEADER_TYPE_0 {
      ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
      ULONG CIS;
      USHORT SubVendorID;
      USHORT SubSystemID;
      ULONG ROMBaseAddress;
      ULONG Reserved2[2];
      UCHAR InterruptLine; 
      UCHAR InterruptPin; 
      UCHAR MinimumGrant; 
      UCHAR MaximumLatency; 
    } type0;
    struct _PCI_HEADER_TYPE_1 {
      ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
      UCHAR PrimaryBusNumber;
      UCHAR SecondaryBusNumber;
      UCHAR SubordinateBusNumber;
      UCHAR SecondaryLatencyTimer;
      UCHAR IOBase;
      UCHAR IOLimit;
      USHORT SecondaryStatus;
      USHORT MemoryBase;
      USHORT MemoryLimit;
      USHORT PrefetchableMemoryBase;
      USHORT PrefetchableMemoryLimit;
      ULONG PrefetchableMemoryBaseUpper32;
      ULONG PrefetchableMemoryLimitUpper32;
      USHORT IOBaseUpper;
      USHORT IOLimitUpper;
      ULONG Reserved2;
      ULONG ExpansionROMBase;
      UCHAR InterruptLine;
      UCHAR InterruptPin;
      USHORT BridgeControl;
    } type1;
  } u;
  UCHAR DeviceSpecific[108];
} PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG;

Members

• VendorID
  PCI vendor identifier register.

• DeviceID
  PCI device identifier register.

• Command
  PCI command register.

• Status
  PCI status register.

• RevisionID
  PCI revision identifier register.

• ProgIf
  PCI programming interface register.

• SubClass
  PCI device sub-class register.

• BaseClass
  PCI device base-class register.

• CacheLineSize
  PCI cache line size register.

• LatencyTimer
  PCI latency timer register.

• HeaderType
  PCI header type register.

  The following table shows possible values.

  Value	Description
  0	Indicates a typical PCI device.
  1	Indicates a PCI-PCI bridge.

• BIST
  PCI built-in self-test register.

• u.type0.BaseAddresses
  Array of PCI base address registers. Typical PCI devices have six base address registers, PCI-to-PCI bridges have two, and PCI-to-CardBus bridges have one.

• u.type0.CIS
  CardBus card information structure (CIS) pointer register.

• u.type0.SubVendorID
  PCI subsystem vendor identifier register.

• u.type0.SubSystemID
  PCI subsystem identifier register.

• u.type0.ROMBaseAddress
  PCI ROM base address register.

• u.type0.Reserved2
  Reserved.

• u.type0.InterruptLine
  PCI interrupt line register.

• u.type0.InterruptPin
  PCI interrupt pin register.

• u.type0.MinimumGrant
  PCI minimum grant register.

• u.type0.MaximumLatency
  PCI maximum latency register.

• u.type1.BaseAddress
  PCI base address register.

• u.type1.PrimaryBusNumber
  PCI primary bus number register.

• u.type1.SecondaryBusNumber
  PCI secondary bus number register.

• u.type1.SubordinateBusNumber
  PCI subordinate bus number.

• u.type1.SecondaryLatencyTimer
  PCI secondary latency timer.

• u.type1.IOBase
  Lower 8 bits of PCI I/O base address register.

• u.type1.IOLimit
  Lower 8 bits of PCI I/O limit address register.

• u.type1.SecondaryStatus
  PCI secondary status register.

• u.type1.MemoryBase
  PCI memory base address register.

• u.type1.MemoryLimit
  PCI memory limit address register

• u.type1.PrefetchableMemoryBase
  Lower 16 bits of PCI prefetchable memory base address register.

• u.type1.PrefetchableMemoryLimit
  Lower 16 bits of PCI prefetchable memory limit address register.

• u.type1.PrefetchableMemoryBaseUpper32
  Upper 32 bits of PCI prefetchable memory base address register.

• u.type1.PrefetchableMemoryLimitUpper32
  Upper 32 bits of PCI prefetchable memory limit address register.

• u.type1.IOBaseUpper
  Upper 16 bits of PCI I/O base address register.

• u.type1.IOLimitUpper
  Upper 16 bits of PCI I/O limit address register.

• u.type1.Reserved2
  Reserved.

• u.type1.ExpansionROMBase
  PCI expansion ROM base address register.

• u.type1.InterruptLine
  PCI interrupt line register.

• u.type1.InterruptPin
  PCI interrupt pin register.

• u.type1.BridgeControl
  PCI bridge control register.

• u.type1.BaseAddress
  PCI base address register.

• DeviceSpecific
  Device specific registers in the PCI configuration space, varies by device.

Remarks

All PCI devices have a common set of registers that include VendorID, DeviceID, and so on.

This structure differs for these PCI devices: header type 0 for devices, and header type 1 for PCI-to-PCI bridges. For more information, see the PCI Local Bus Specification, revision 2.1 or 2.2.

Requirements

See Also

Reference

PCI Bus Driver Structures