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MIPS Microprocessor

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MIPS interrupt service routines (ISRs) are limited to using a subset of the available microprocessor registers. Specifically, a MIPS ISR can only use registers AT, V0, A0, A1, A2, and A3. Use the following design principals when creating an OAL for a MIPS microprocessor:

  • The ISR must return by means of jra.

  • Implement a system-timer ISR that increments the variable CurMSec.

  • OEMInit needs to register the system-timer ISR.

  • Create the OAL function GetTickCount to return a value from the system timer.

  • The OEMIdle function takes a single parameter that is only used by the MIPS CPU.

    This parameter is undefined for other CPUs. It is the base program status register (PSR) value and sets interrupts to be enabled. The following code example shows how OEMIdle is defined for the MIPS microprocessor.

    void OEMIdle(DWORD dwIdleParam);

  • Nested interrupts.

    The MIPS kernel utilizes a structure that provides information about which nested interrupts are masked while the current interrupt is being handled. To gain access to this structure, the IntrPrio global variable must be declared in the OAL.

See Also

How to Develop an OEM Adaptation Layer | Microprocessor-specific Issues

Last updated on Wednesday, April 13, 2005

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