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SH-4 Epilog (Windows Embedded CE 6.0)

  • Article

1/5/2010

The SH-4 epilog is a contiguous sequence of instructions that restores the saved permanent registers, resets the stack pointer to its value on function entry, and returns to the function's calling function.

In addition, the Virtual Unwinder requires the epilog to have the following parts, except where noted:

  1. A single add instruction that increments the frame pointer. This instruction must immediately precede the sequence of instructions defined for part 2. (Optional)
  2. A sequence of instructions that modify R15 by referencing it in the destination operand of the instruction or in a post-increment memory address operand of the instruction. This sequence immediately precedes the rts instruction of part 3. All instructions in this sequence must be lds, mov, fmov, fschg, or add instructions.
    This item is optional. It does not appear in functions that have no RSA area to restore.
  3. The rts instruction and its delay slot instruction. The instruction in the delay slot of the rts is considered part of the epilog but is not required to conform to the rules listed for item 2.

When unwinding out of a function, the Virtual Unwinder must determine if the currently executing instruction is in the prolog or epilog. If the current point of control is in the prolog or in the epilog, the Virtual Unwinder must take special measures to unwind out of the function.

The following list shows three conditions that the Virtual Unwinder must maintain:

  • If the function establishes a frame pointer, the function may not modify the frame pointer value during the interval between the completion of the last prolog instruction and the beginning of the first instruction of the epilog.
    If the function does not establish a frame pointer, the function must not modify value in R15 during the interval between the completion of the last prolog instruction and the beginning of the first instruction of the epilog.
  • The address contained in the stack pointer, which is always R15, must never be greater than the lowest address of any unrestored register value in the Register Save Area.
  • The SZ, PR, and FR bits of the FPSCR register must always be set to zero on entering and exiting the prolog and epilog. The PR and FR bits must not be modified within the prolog or epilog. This condition enables the Virtual Unwinder to correctly reverse-execute floating-point instructions.

See Also

Concepts

SH-4 Prolog
SH-4 Prolog and Epilog Examples

Other Resources

Renesas SH-4 Prolog and Epilog